DragonFly crash over Vaio NR21Z
Matthew Dillon
dillon at apollo.backplane.com
Sat May 17 10:23:08 PDT 2008
:This is a long post. Kept it on Users (where it started), and because
:I'm hoping others here might be able to tell us whether or not their
:systems use the same Texas Instruments OHCI Compliant IEEE 1394 Host
:Controller I have in my system (vendor=104c, dev=803a), and if they are
:also having issues with it.
:...
:... this thread is a hit on the VAIO NR notebook side of the error
:... and the firewire thread from November 2004 on the kernel list
:(between Matt & Gabor MICSKO) hits the details.
: [[
:http://leaf.dragonflybsd.org/mailarchive/kernel/2004-11/msg00037.html
:]]
:
: fwohci0: EUI64 08:00:46:03:02:83:de:3e
: NMI ISA a1, EISA ff
: RAM parity error, likely hardware failure
:
: Fatal trap 19: non-maskable interrupt trap while in kernel mode
: instruction pointer = 0x8:0xc020e7be
: stack pointer = 0x10:0xc07789f8
: frame pointer = 0x10:0xc0778a14
: code segment = base 0x0, limit 0xfffff, type 0x1b
: = DPL 0, pres 1, def32 1, gran 1
: processor eflags = interupt enabled, IOPL = 0
: current process = 0 (swapper)
: current thread - pri 12
:
: kernel: type 19 trap, code=0
: Stopped at fwphy_rddata+0x96: testw %bx, %bx
:...
:Any thoughts, or similar experiences?
:
:--David
This looks like a case of the driver accessing on-device memory
which has not yet been initialized. That is, the parity error is
not due to your RAM, but a PCI bus parity error due to bug in the
device initialization sequence.
Hmm. One thing I see right off the bat is that the FreeBSD driver
does have an extra DELAY(500) in the probe code. Try this patch.
-Matt
Index: fwohci.c
===================================================================
RCS file: /cvs/src/sys/bus/firewire/fwohci.c,v
retrieving revision 1.17
diff -u -p -r1.17 fwohci.c
--- fwohci.c 20 Apr 2008 13:44:25 -0000 1.17
+++ fwohci.c 17 May 2008 17:18:08 -0000
@@ -426,6 +426,8 @@ * number of port supported by core-l
* It is not actually available port on your PC .
*/
OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
+ DELAY(500);
+
reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
if((reg >> 5) != 7 ){
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