boot loader question

Bill Hacker wbh at
Tue Apr 5 11:03:33 PDT 2005> <20050405084741.GA3491 at xxxxxxxxxxxxxxxxx> <200504051700.j35H0jtp084880 at xxxxxxxxxxxxxxxxxxxx>
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Matthew Dillon wrote:

> :
> :On Tue, Apr 05, 2005 at 04:32:28PM +0800, Bill Hacker wrote:
> :> Again - 'shared interrupts' have us going out in software and burning 
> :> CPU-cycles
> :> to inquire as to who wishes to do what, with which, and to whom each 
> :> time one line goes active.
> :
> :Actually it is not more expensive than doing the PCI cycles in hardware,
> :just more expensive to manufacture.
> :
> :> Were the INT lines to be read as a byte, or even a nibble, we could 
> :> decode that
> :> in a gate array and save a lot of time and code execution.
> :
> :But it would also increase the costs of the bus protocol dramatically.
> :Keep in mind that PCI interrupts are additive (level triggered?),
> :read as long as any device has the interrupt triggered, the system
> :can handle it. It's the simplest and most efficient way to avoid
> :races without additional bus cycles, which can often be even more
> :expensive.
> :
> :Joerg
>     If Intel had adopted Motorola's vector generation protocool it wouldn't
>     be the problem it is today.  Motorola's 68000 had prioritized level
>     triggered interrupts with individual vectoring capabilities.   The
>     glue logic required consisted of a single 14-pin 8:3 priority mux
>     dip chip.

Shades of VME vs Multibus...

Pardon Intel, Matthew, for they are but barbarians, and think that the 
customs of their mask and and die are the laws of nature.

(With apologies to GBS) ;-)

>     But since we can't redesign the protocols....
> 					-Matt
> 					Matthew Dillon 
> 					<dillon at xxxxxxxxxxxxx>

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