boot loader question
wbh at conducive.org
Tue Apr 5 03:04:25 PDT 2005
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Joerg Sonnenberger wrote:
> On Tue, Apr 05, 2005 at 04:32:28PM +0800, Bill Hacker wrote:
>>in a gate array and save a lot of time and code execution.
> But it would also increase the costs of the bus protocol dramatically.
Not at all. Decrease it.
> Keep in mind that PCI interrupts are additive (level triggered?),
Open collector/wired OR .. or the functional equivalent.
not too different from S-100 or Q-bus.
(Not that there is a lot of difference at current bus speeds!)
Nor does it matter if they were bit-patterns on a serial optical bus
or parallel copper traces on a MB or conductors on the chip.
The point is that we have provided too few *unique* states.
We map memory and I/O to the architecture - 16, 32, 64 bit
- yet allow only a miniscule fraction of that for interrupts,
requiring 'sharing' which in turn requires an inquiry process
to sort *which* of the shared devices is to be serviced.
We could have had 64 unique IRQ's way back then, and 256 unique IRQ's
now, for next to no cost.
32K hardware IRQ's is probably overkill - then again, IBM PC1 seemed to
think 8 were too many.
> read as long as any device has the interrupt triggered,
> the system can handle it.
. ..with a good deal of software, i.e. sense INT is high, scan for which
device(s), did/are doing that, chat with them,
lookup what is needed to service them, clear the IRQ ...and other things.
Too much of it is in software, when fractional cents worth of silicon
and copper could have made the job easier by providing more info up front.
> It's the simplest and most efficient way to avoid
> races without additional bus cycles, which can often be even more
The need for prioritization, queueing, avoiding races and such doesn't
magically disappear, but having more unique info from the hardware at
first instance can make management simpler and faster.
But this is not a DragonFly issue, so I will shut up about it. ;-)
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