Multiple queues support for GigE

[Sepherosa Ziehau]

Hi all,

GigE drivers support multiple queues:

bnx(4)    Broadcom 5718/57785 family

    All chips supported by this driver support 4 RX queues.
    5719/5720/5717C support 4 TX queues.

    For more information:
    http://leaf.dragonflybsd.org/cgi/web-man/?command=bnx&section=ANY

    * For folks with NetBSD/OpenBSD backgroud, this driver is not
      NetBSD/OpenBSD's bnx(4)

bce(4)    Broadcom NetExtremeII

    Only 5709/5716 supported by this driver support 8 RX queues and 8
    TX queues.

    For more information:
    http://leaf.dragonflybsd.org/cgi/web-man/?command=bce&section=ANY

    * For folks with NetBSD/OpenBSD backgroud, this driver is not
      NetBSD/OpenBSD's bce(4)

emx(4)    Intel PRO/1000 (first generation?)

    All chips supported by this driver support 2 RX queues.
    82571/82572 could enable 2 TX queues in polling(4) mode.

    For more information:
    http://leaf.dragonflybsd.org/cgi/web-man/?command=emx&section=ANY

igb(4)    Intel PRO/1000 (second generation?)

    Various chips have different number of RX/TX queues.  Commonly used
    chips, like 82580 and I350, support 8 RX queues and 8 TX queues.

    One thing worth noting is that for 82576 at most 16 RX queues and
    16 TX queues could be enable in polling(4) mode.

    For more information:
    http://leaf.dragonflybsd.org/cgi/web-man/?command=igb&section=ANY

jme(4)   JMicron JMC250/JMC260

    All chips supported by this driver support 4 RX queues.

    For more information:
    http://leaf.dragonflybsd.org/cgi/web-man/?command=jme&section=ANY

To use multiple TX queues, you don't need to disable ALTQ from the
kernel configuration and there is no special kernel options are needed.
However, if you enable any ALTQ packet scheduler through pf(4), only
one TX queue will be used by the network stack.

Another thing needs to be noted about is multiple TX queues and TSO:
All chips supporting multiple TX queues use round-robin arbitration
between TX queues.  For most of the chips, the round-robin arbitration
is on TSO packet boundary.  Only chips supported by the igb(4) (except
82575) round-robin arbitrate on TCP segment boundary.

Each driver has its own tunables to configure number of RX and TX
queues MSI-X leading CPU and etc.  Please refer to the manpage for
detailed information.

Best Regards,
sephe

-- 
Tomorrow Will Never Die
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