copying pkgsrc tree around jails on beefy machine - fast on 2nd iteration, a bit slower than first on 3rd iteration

[Matthew Dillon]

:thanks for that info.
:
:btw, how's the address space split beetween on dragonfly?
:On linux/x86 is kernel 1GB, app: 3GB
:on windows/x86 is kernel 2GB, apps: 2GB, supposadly tunnable, but I
:couldn't get the 1:3 split I needed on win2k nor winXP.
:I don't know how's that on BSD systems...

    3G for apps, 1G for the kernel.  Cached VM pages do not have to be
    mapped into the kernel, so the kernel can still cache > 1GB of memory.
    But all kernel memory data structures do have to mapped to kernel
    memory, as well as the PCI bus address space (which itself can eat a
    lot of memory especially if you have a video card with lots of video
    memory).

    The problem that all PC operating systems face is that available kernel
    memory is fixed so kernel data structure limits do not scale with
    actual physical memory past a certain point.  The tradeoff
    can be adjusted with a kernel build option.

:Just has a reminder, kernel and apps don't share virtual address
:space, but they somehow have this split because of performance issues
:with flushing the TLB on every kernel call, I think where are also
:some problems with some drivers memory mappings, PCI and DMA mappings
:also, am I by any chance correct?
:
:TIA,
:
:--
:Miguel Sousa Filipe

    Almost right.  The kernel and app(s) *DO* share the same virtual
    address space (hence the 3G/1G split).  It is simply that the app(s)
    are not allowed to access the kernel address space because the kernel
    pages are marked supervisor-only.  Each application has its own virtual
    address space but the high 1GB is mapped to the (same) kernel memory.
    This involves fairly minimal work.

    The jist of all of this is that the top 1GB is always kernel memory
    no matter what is running.

    This allows the app to enter into the kernel and for the kernel to
    return to the app without having to change the MMU base pointer, thus
    avoiding TLB flushes.  A TLB flush occurs whenever the MMU base pointer
    is changed.

    It *IS* possible to separate the address spaces using the processor
    TSS, which is basically a hardware-supported 'context', but the
    performance penalties are horrendous which is why nobody uses it
    for anything other then emulation of older PC's (e.g. 8086, 80826).

    Intel originally conceived of the TSS as a means of switching between
    'tasks', but it was at a time when processors where much slower and
    the microcode overhead of the TSS support was no worse then doing it
    with normal instructions.  These days processors are much faster and
    heavily optimized to execute normal instructions, and anything that
    runs microcode introduces huge performance penalties.
 
					-Matt
					Matthew Dillon 
					<dillon at xxxxxxxxxxxxx>