No subject

Wed Jun 29 02:24:57 PDT 2016


Disabling a Local APIC Disables Both Logical Processor APICs on a 
Hyper-Threading Technology Enabled Processor

Problem: Disabling a local APIC on one logical processor of a 
Hyper-Threading Technology enabled processor by clearing bit 11 of the 
IA32_APIC_BASE MSR will effectively disable the local APIC on the other 
logical processor

Implication: Disabling a local APIC on one logical processor prevents 
the other logical processor from sending or receiving interrupts. 
Multiprocessor Specification compliant BIOSs and multiprocessor 
operating systems typically leave all local APICs enabled preventing any 
end-user visible impact from this erratum.

Workaround: Do not disable the local APICs in a Hyper-Threading 
Technology enabled processor.

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Problem:  When a system bus agent (processor or chipset) issues an 
interrupt transaction without data onto the system bus and the 
transaction receives a HardFailure response, a potential processor hang 
can occur.

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