Testers with sili(4) hardware needed

[Francois Tigeot]

Hi,

I'm trying to make sure the Silicon Image SATA chipsets can properly
handle I/O requests of 256KB (their apparent theoretical limit). 

If you use this hardware, could you please apply the attached patch and
report your findings ?

Running this command as root will generate 256KB I/O requests:

    dd if=/dev/da0 of=/dev/null bs=1m count=10k

I'm also interested if there is any issue in the course of regular
operation.

Thanks!

-- 
Francois Tigeot
-------------- next part --------------
diff --git a/sys/cpu/i386/include/param.h b/sys/cpu/i386/include/param.h
index d6547ce..2f48017 100644
--- a/sys/cpu/i386/include/param.h
+++ b/sys/cpu/i386/include/param.h
@@ -121,7 +121,7 @@
 #define BLKDEV_IOSIZE	PAGE_SIZE	/* default block device I/O size */
 #endif
 #define DFLTPHYS	(64 * 1024)	/* default max raw I/O transfer size */
-#define MAXPHYS		(128 * 1024)	/* max raw I/O transfer size */
+#define MAXPHYS		(256 * 1024)	/* max raw I/O transfer size */
 #define MAXDUMPPGS	(MAXPHYS/PAGE_SIZE)
 
 #define IOPAGES	2		/* pages of i/o permission bitmap */
diff --git a/sys/cpu/x86_64/include/param.h b/sys/cpu/x86_64/include/param.h
index 15a489d..23a5e04 100644
--- a/sys/cpu/x86_64/include/param.h
+++ b/sys/cpu/x86_64/include/param.h
@@ -143,7 +143,7 @@
 #define BLKDEV_IOSIZE	PAGE_SIZE	/* default block device I/O size */
 #endif
 #define DFLTPHYS	(64 * 1024)	/* default max raw I/O transfer size */
-#define MAXPHYS		(128 * 1024)	/* max raw I/O transfer size */
+#define MAXPHYS		(256 * 1024)	/* max raw I/O transfer size */
 #define MAXDUMPPGS	(MAXPHYS/PAGE_SIZE)
 
 #define IOPAGES	2		/* pages of i/o permission bitmap */
diff --git a/sys/dev/disk/sili/sili.h b/sys/dev/disk/sili/sili.h
index 8f89419..6ce701a 100644
--- a/sys/dev/disk/sili/sili.h
+++ b/sys/dev/disk/sili/sili.h
@@ -629,18 +629,19 @@ struct sili_sge {
 #define SILI_SGE_FLAGS_XCF	0x10000000	/* external cmd fetch	*/
 
 /*
- * Each sge is 16 bytes.  We need to accomodate MAXPHYS (128K) which is
- * at least 32 entries, plus one for page slop, plus one more for every
- * 3 entries for the link entry.
+ * Each sge is 16 bytes.
  *
  * We want our prb structure to be power-of-2 aligned (it is required to be
  * at least 8-byte aligned).  the prb base header is 4 SGE's but includes 2
  * SGE's within it.
+ * The prb structure also can't cross a 64KB boundary, and thus can only
+ * have a maximum size of 65536 / 16 / 32  == ~128 entries (128 - 4)
  */
-#define SILI_MAX_SGET		(64 - 4)
+#define SILI_MAX_SGET		(128 - 4)
 #define SILI_MAX_PMPORTS	16
+#define SILI_MAXPHYS		(256 * 1024)	/* 256 KB */
 
-#if MAXPHYS / PAGE_SIZE + 1 > (SILI_MAX_SGET * 3 / 4)
+#if SILI_MAXPHYS / PAGE_SIZE + 1 > (SILI_MAX_SGET * 3 / 4)
 #error "SILI_MAX_SGET is not big enough"
 #endif
 
diff --git a/sys/dev/disk/sili/sili_cam.c b/sys/dev/disk/sili/sili_cam.c
index cd6e69f..99fc1c8 100644
--- a/sys/dev/disk/sili/sili_cam.c
+++ b/sys/dev/disk/sili/sili_cam.c
@@ -872,6 +872,7 @@ sili_xpt_action(struct cam_sim *sim, union ccb *ccb)
 		ccb->cpi.transport_version = 1;
 		ccb->cpi.protocol = PROTO_SCSI;
 		ccb->cpi.protocol_version = SCSI_REV_2;
+		ccb->cpi.maxio = SILI_MAXPHYS;
 
 		ccbh->status = CAM_REQ_CMP;
 		if (ccbh->target_id == CAM_TARGET_WILDCARD) {