GSoC: Add SMT/HT awareness to DragonFlyBSD scheduler

Chris Turner c.turner at
Wed Aug 1 00:14:15 PDT 2012

Awesome work! Look forward to trying it out.

On 07/29/12 13:01, Mihai Carabas wrote:
> Here is an interesting CPU topology from a dual-socket XEON:

Is this correct?

e.g.: CHIP0 has cores 0,1,2,8,9,10 and so does CHIP1,
   but there is no core labelled 3,4,5,6,7 and 11
also the cpu numbering seems 'staggered' to me -
   e.g. chip0/core0/{cpu1,cpu13) and chip1/core0/{cpu0,cpu12}
rather than something more like:
   chip0/core0-5/cpu0-11 & chip1/core6-11/cpu12-23

Disclaimer: haven't read the code, etc - just thought I'd ask esp.
since the benchmarks around the same time as you sent this mail
seemed to show inconclusive results - perhaps discovery issues are
translating to problems in the scheduler or something.

2c from the peanut gallery

Good luck & continued success!


- Chris

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