SMP/UP kernel S01E02

[Matthew Dillon]

:Matthew Dillon wrote:
:>     Only newer cpus have APICs and IOAPICs regardless of whether they
:>     are SMP-capable or not.  Older ones do not.
:
:Afaik, at least any CPU since the Pentium has a LAPIC; and perhaps some 
:late 486 models as well; as for IOAPICs, that's a feature of mainboard 
:chipsets.
:
:Cheers,
:-- 
:         Thomas E. Spanjaard
:         tgen at netphreax.net

    If you can't route interrupts to the LAPIC, its nothing more then a
    glorified counter.  In order to use the LAPIC for interrupt handling
    either the IOAPIC has to be routed to the LAPIC, or the PIC has to be
    routed to the LAPIC, or both.  If the BIOS doesn't do that magic,
    the LAPIC is basically unusable.

    On AMD systems the PIC EXTINT/NMI is usually routed over the
    hypertransport bus, and the BIOS programs hardware registers in the
    protected PCI configuration space (0xcf8-0xcff) to route that
    EXTINT/NMI to the LAPIC.  The BIOS does not usually do this on UP
    systems, or it only does it with certain ACPI magic (I'm not really
    sure, the APIs are pretty aweful).

    At least on AMD systems it is usually possible to route the PIC to
    the LAPIC if the BIOS doesn't, due to the hypertransport standard.
    I have no clue how to do it on Intel systems.

    If you can't route the PIC to the LAPIC then the PICs interrupt goes
    directly into the cpu's EXTINT/NMI circuitry, meaning that you have
    to handle the interrupt via the cpu's base interrupt vectors instead
    of via the LAPICs interrupt vectors.

						-Matt