PAE with dragonfly
kachun at pathlink.com
Thu Jun 9 09:18:04 PDT 2005
"David Rhodus" <sdrhodus at xxxxxxxxx> wrote in message
news:fe77c96b05060812014797aa3e at xxxxxxxxxxxxxxxxx
> On 6/8/05, Craig Dooley <xlnxminusx at xxxxxxxxx> wrote:
>> Doesn't AMD64 use PAE for large address spaces? I thought the Page
>> Table structures were the same for both.
> No, on AMD64 when operating in long mode the address space is 64bit.
> PAE is a 32bit hack that lets you access a few more bits. 34, 37 ? I
> don't recall exactly off the top of my head.
> There are some interesting uses for PAE on the regular ia32
> architecture such as allowing the kernel a full 4Gig memory and the
> userland a full 4Gig of memory. This actually makes the kernels life
> a lot easier, though almost no one has this type of setup so its
> mostly a moot development point. About a year ago I had a working
> implementation of PAE working on DragonFly, though I only had one test
> machine with 4.5 Gigs of memory. I also only had access to the
> machine for a few days so I never had time to go through and optimize
> the code.
> I can look around for the old patch if someone has access to some
> machines with more than 4 gigs of memory and someone that also has
> time to revive it.
I have a dual Xeon system with 6G RAM sitting on my bench that I can use.
For our application, I will need to get the twe driver to be PAE 'safe'
also, but I have some time that I can spend on this project.
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