mtd_cpl question

Joerg Sonnenberger joerg at
Thu Jun 2 10:30:04 PDT 2005

On Thu, Jun 02, 2005 at 10:13:10AM -0700, Matthew Dillon wrote:
>    Have you taken a look at the SPL masks recently?  Just about all major
>    devices are covered by the most basic SPL anyway, so for all intents and
>    purposes a splbio() or splvm() is going to be equivalent to a critical 
>    section.

splbio and splbio for example don't interlock. We already have a slow
disk IO path, when e.g. network driver can prevent the processing
of the ATA interrupt, this will even suck more.

>    Also, keep in mind that the cpu is going to be executing instructions
>    no matter what while in an SPL or critical section... whether they 
>    are mainline instructions or interrupt instructions.  The only issue
>    is interrupt *latency*, not so much cpu efficiency, and frankly SPLs 
>    are not held long enough for interrupt latency to be effected virtually
>    at all, and even then we are only talking about a few microseconds at
>    worst.

There is a lot of code issuing DELAYs under spl protection. For example,
almost all MII operations are running in the area of 20ms with common
NICs. Those are ages on a modern CPU. Yes, this about latency. But not
serving interrupts for a long time for _any_ device *does* hurt.


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