DragonFly and FBSD 5.1

Mike Hibler mike at flux.utah.edu
Mon Oct 27 14:38:13 PST 2003

> From: Soren Schmidt <sos at xxxxxxxxxxxxxxxxxx>
> Subject: Re: DragonFly and FBSD 5.1
> To: "Jeroen Ruigrok/asmodai" <asmodai at xxxxxx>
> Date: Mon, 27 Oct 2003 22:45:30 +0100 (CET)
> It seems Jeroen Ruigrok/asmodai wrote:
> > -On [20031027 22:32], Soren Schmidt (sos at xxxxxxxxxxxxxxxxxx) wrote:
> > >That patch is bogus, it doesn't work.
> > >I've told that over and over on the lists and in several semilar PR's.
> > >For working code, look in -current...
> > 
> > Mmm, then at least it is a work around.  I am guessing here that old ATA
> > code makes assumptions about the highest available DMA mode and tries to
> > set it to that and just hangs when it cannot set that.  At least I can
> > now normally boot.  Now I can more easily work on getting it fixed as it
> > should be fixed then.
> You are relying on the BIOS to have setup the chipset correctly for
> the mode you happen to use, ie *pure chance* :)
> What should be dealt with is the faulty support of non-known chips,
> but I'll bite and admit I havn't even fixed that in -current yet :)

Are you talking specifically about the ATA patch, and the implementation
of UDMA6 (or ATA133 or whatever you would call it)?

Yeah, I just guessed at that.  I thought I mentioned that in the PR,
but alas I didn't, sorry!  I should know better.

I would think your odds are considerably better than *pure chance* since
you and the BIOS presumably want the highest possible transfer rate,
but your point is well taken.

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