git: NVMM: Sync with NetBSD #2: SVM & VMX backends
aly at crater.dragonflybsd.org
Tue Jul 20 16:30:22 PDT 2021
Author: Aaron LI <aly at aaronly.me>
Date: Sun Jun 27 07:58:06 2021 +0800
NVMM: Sync with NetBSD #2: SVM & VMX backends
This commit syncs the NVMM kernel part to match NetBSD current (as of
2021-06-25). The main changes are as follows:
* Improve host FPU handling. The host FPU state is now save in PCB
instead of in vCPU data area.
* Clear TS flag from the host's CR0 in _vcpu_init(), because it is also
cleared inside the _vcpu_run() loop. Not clearing it could trigger
DNAs on VMEXITs.
* Set VMCS_HOST_IDTR_BASE on each CPU independently, because the IDT is
now per-CPU (in NetBSD).
NOTE: DragonFly is also using per-CPU IDT, so this change fixes a
* Disable interrupts earlier to prevent possible race against TLB flush
IPIs, because such IPIs don't respect the IPL, so enforcing IPL_HIGH
has no effect.
* VMX: Improve CR0 handling:
- Flush the guest TLB when certain CR0 bits change.
- Employ VMCS_CR0_SHADOW to allow the guest to update certain static
CR0 bits. Guest gets the illusion that the CR0 change was applied,
but the "real" CR0 bits remain unchanged.
- Force CR0_ET to 1 in shadow CR0; force CR0_ET and CR0_NE in real
- Add comments to clarify better.
NetBSD has overhauled the FPU handling, so NVMM no longer needs to save
host FPU state in the _cpudata structure. I haven't found a way to do
this on DragonFly yet, so leave it and investigate it later.
Summary of changes:
sys/dev/virtual/nvmm/nvmm.c | 2 +-
sys/dev/virtual/nvmm/nvmm_compat.h | 7 +-
sys/dev/virtual/nvmm/x86/nvmm_x86_svm.c | 43 ++++++----
sys/dev/virtual/nvmm/x86/nvmm_x86_svmfunc.S | 6 --
sys/dev/virtual/nvmm/x86/nvmm_x86_vmx.c | 122 ++++++++++++++++++----------
sys/dev/virtual/nvmm/x86/nvmm_x86_vmxfunc.S | 11 ---
6 files changed, 109 insertions(+), 82 deletions(-)
DragonFly BSD source repository
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