git: pc64: An mfence is supposed to suffice for TSC_DEADLINE vs. xAPIC ordering.

Tue Sep 5 13:11:25 PDT 2017

commit 315d99390764f1b7ed4b020a9942a11aab550c79
Author: Imre VadÃ¡sz <imre at vdsz.com>
Date:   Tue Sep 5 22:06:34 2017 +0200

    pc64: An mfence is supposed to suffice for TSC_DEADLINE vs. xAPIC ordering.
    
    * I accidentally used a too old version of the intel sdm documentation,
      which still described that complicated serialization method, but newest
      documentation claims that an mfence should be used for serializing the
      xAPIC write vs. the wrmsr to the TSC_DEADLINE register.

Summary of changes:
 sys/platform/pc64/apic/lapic.c | 17 +----------------
 1 file changed, 1 insertion(+), 16 deletions(-)

http://gitweb.dragonflybsd.org/dragonfly.git/commitdiff/315d99390764f1b7ed4b020a9942a11aab550c79


-- 
DragonFly BSD source repository