cvs commit: src/sys/dev/disk/aic7xxx ahc_eisa.c ahc_pci.c ahd_pci.c aic7770.c aic79xx.c aic79xx.h aic79xx.seq aic79xx_inline.h aic79xx_osm.c aic79xx_osm.h aic79xx_pci.c aic7xxx.c aic7xxx.h aic7xxx.reg aic7xxx.seq aic7xxx_93cx6.c ...

Peter Avalos pavalos at
Thu Jul 5 17:02:35 PDT 2007

pavalos     2007/07/05 17:01:16 PDT

DragonFly src repository

  Modified files:
    sys/dev/disk/aic7xxx ahc_eisa.c ahc_pci.c ahd_pci.c aic7770.c 
                         aic79xx.c aic79xx.h aic79xx.seq 
                         aic79xx_inline.h aic79xx_osm.c 
                         aic79xx_osm.h aic79xx_pci.c aic7xxx.c 
                         aic7xxx.h aic7xxx.reg aic7xxx.seq 
                         aic7xxx_93cx6.c aic7xxx_inline.h 
                         aic7xxx_osm.c aic7xxx_osm.h aic7xxx_pci.c 
  Added files:
    sys/dev/disk/aic7xxx aic_osm_lib.c aic_osm_lib.h 
  	Use common OSM routines from aic_osm_lib for bus dma operations,
  	delay routines, accessing CCBs, byte swapping, etc.
  	Provide a better description for the 2915/30LP on attach.
  	To speed up non-packetized CDB delivery in Rev B, all CDB
  	acks are "released" to the output sync as soon as the
  	command phase starts.  There is only one problem with this
  	approach.  If the target changes phase before all data are
  	sent, we have left over acks that can go out on the bus in
  	a data phase.  Due to other chip contraints, this only
  	happens if the target goes to data-in, but if the acks go
  	out before we can test SDONE, we'll think that the transfer
  	has completed successfully.  Work around this by taking
  	advantage of the 400ns or 800ns dead time between command
  	phase and the REQ of the new phase.  If the transfer has
  	completed successfully, SCSIEN should fall *long* before we
  	see a phase change.  We thus treat any phasemiss that
  	occurs before SCSIEN falls as an incomplete transfer.
  		Add the AHD_FAST_CDB_DELIVERY feature.
  		Set AHD_FAST_CDB_DELIVERY for all Rev. B parts.
  		Test for PHASEMIS in the command phase for
  		all AHD_FAST_CDB_DELIVERY controlelrs.
  	Move definition of controller BAR offsets to core header files.
  	In the softc free routine, leave removal of a softc from the
  	global list of softcs to the OSM (the caller of this routine).
  	This allows us to avoid holding the softc list_lock during device
  	destruction where we may have to sleep waiting for our recovery
  	thread to halt.
  	Use ahc_pci_test_register access to validate I/O mapped in
  	addition to the tests already performed for memory mapped
  	Remove unused ahc_power_state_change() function.
  	Remove reduntant definition of controller BAR offsets.  These
  	are also defined in aic79xx.h.
  	Remove unused ahd_power_state_change() function.
  	Move timeout handling to the driver cores.  In the case
  	of the aic79xx driver, the algorithm has been enhanced
  	to try target resets before performing a bus reset.  For
  	the aic7xxx driver, the algorithm is unchanged.  Although
  	the drivers do not currently sleep during recovery (recovery
  	is timeout driven), the cores do expect all processing to
  	be performed via a recovery thread.  Our timeout handlers
  	are now little stubs that wakeup the recovery thread.
  	Change shared_data allocation to use a map_node so
  	that the sentinel hscb can use this map node in
  	ahd_swap_with_next_hscb.  This routine now swaps
  	the hscb_map pointer in additon to the hscb
  	contents so that any sync operations occur on
  	the correct map.
  	physaddr -> busaddr
  	Pointed out by: Jason Thorpe <thorpej at>
  	Make more use of the in/out/w/l/q macros for accessing
  	byte registers in the chip.
  	Correct some issues in the ahd_flush_qoutfifo() routine.
  	    o Run the qoutfifo only once the command channel
  	      DMA engine has been halted.  This closes a window
  	      where we might have missed some entries.
  	    o Change ahd_run_data_fifo() to not loop to completion.
  	      If we happen to start on the wrong FIFO and the other
  	      FIFO has a snapshot savepointers, we might deadlock.
  	      This required our delay between FIFO tests to be
  	      moved to the ahd_flush_qoutfifo() routine.
  	    o Update/add comments.
  	    o Remove spurious test for COMPLETE_DMA list being empty
  	      when completing transactions from the GSFIFO with
  	      residuals.  The SCB must be put on the COMPLETE_DMA
  	      scb list unconditionally.
  	    o When halting command channel DMA activity, we must
  	      disable the DMA channel in all cases but an update
  	      of the QOUTFIFO.  The latter case is required so
  	      that the sequencer will update its position in the
  	      QOUTFIFO.  Previously, we left the channel enabled
  	      for all "push" DMAs.  This left us vulnerable to
  	      the sequencer handling an SCB push long after that
  	      SCB was already processed manually by this routine.
  	    o Correct the polarity of tests involving
  	      ahd_scb_active_in_fifo().  This routine returns
  	      non-zero for true.
  	Return to processing bad status completions through
  	the qoutfifo.  This reduces the time that the sequencer
  	is kept paused when handling transactions with bad
  	status or underruns.
  	When waiting for the controller to quiece selections,
  	add a delay to our loop.  Otherwise we may fail to wait
  	long enough for the sequencer to comply.
  	On H2A4 hardware, use the slow slewrate for non-paced
  	transfers.  This mirrors what the Adaptec Windows
  	drivers do.
  	On the Rev B. only slow down the CRC timing for
  	older U160 devices that might need the slower timing.
  	We define "older" as devices that do not support
  	packetized protocol.
  	Wait up to 5000 * 5us for the SEEPROM to become unbusy.
  	Write ops seem to take much longer than read ops.
  	For controllers with the FAINT_LED bug, turn the diagnostic
  	led feature on during selection and reselection.  This covers
  	the non-packetized case.  The LED will be disabled for
  	non-packetized transfers once we return to the top level idle
  	loop.  Add more comments about the busy LED workaround.
  	Extend a critical section around the entire
  	command channel idle loop process.  Previously
  	the portion of this handler that directly manipulated
  	the linked list of completed SCBs was not protected.
  	This is the likely cause of the recent reports of
  	commands being completed twice by the driver.
  	Extend critical sections across the test for,
  	and the longjump to, longjump routines.  This
  	prevents the firmware from trying to jump to
  	a longjmp handler that was just cleared by the
  	Improve the locations of several critical section
  	begin and end points.  Typically these changes
  	remove instructions that did not need to be
  	inside a critical section.
  	Close the "busfree after selection, but before busfree
  	interrupts can be enabled" race to just a single sequencer
  	instruction.  We now test the BSY line explicitly before
  	clearing the busfree status and enabling the busfree
  	Close a race condition in the processing of HS_MAILBOX
  	updates.  We now clear the "updated" status before the
  	copy.  This ensures that we don't accidentally clear
  	the status incorrectly when the host sneaks in an update
  	just after our last copy, but before we clear the status.
  	This race has never been observed.
  	Don't re-enable SCSIEN if we lose the race to disable SCSIEN
  	in our interrupt handler's workaround for the RevA data-valid
  	too early issue.
  	Add comments indicating that the order in which bytes are
  	read or written in ahd_inw and ahd_outw is important.  This
  	allows us to use these inlines when accessing registers with
  	The 29320 and the 29320B are 7902 not 7901 based products.
  	Correct the driver banner.
  	Enable the use of the auto-access pause feature
  	on the aic7870 and aic7880.  It was disabled due
  	to an oversight.
  	avoid leaving garbage in MWI_RESIDUAL.  This
  	prevents spurious overflows whn operating target
  	mode on controllers that require the MWI_RESIDUAL
  	AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag.
  	Reference the correct softc field when testing
  	for its presence.
  	Set the NOT_IDENTIFIED and NO_CDB_SENT bits
  	in SEQ_FLAGS to indicate that the nexus is
  	invalid in await busfree.
  	Add support for the C56/C66 versions of the EWEN and EWDS
  	Move test for the validity of left over BIOS data
  	to ahc_test_register_access().  This guarantees that
  	any left over CHIPRST value is not clobbered by our
  	register access test and lost to the test that was
  	in ahc_reset.
  Obtained-from: FreeBSD
  Revision  Changes    Path
  1.7       +3 -3      src/sys/dev/disk/aic7xxx/ahc_eisa.c
  1.10      +24 -48    src/sys/dev/disk/aic7xxx/ahc_pci.c
  1.9       +9 -48     src/sys/dev/disk/aic7xxx/ahd_pci.c
  1.8       +3 -3      src/sys/dev/disk/aic7xxx/aic7770.c
  1.18      +672 -413  src/sys/dev/disk/aic7xxx/aic79xx.c
  1.6       +29 -15    src/sys/dev/disk/aic7xxx/aic79xx.h
  1.5       +106 -39   src/sys/dev/disk/aic7xxx/aic79xx.seq
  1.5       +41 -28    src/sys/dev/disk/aic7xxx/aic79xx_inline.h
  1.15      +32 -327   src/sys/dev/disk/aic7xxx/aic79xx_osm.c
  1.9       +19 -308   src/sys/dev/disk/aic7xxx/aic79xx_osm.h
  1.9       +48 -59    src/sys/dev/disk/aic7xxx/aic79xx_pci.c
  1.15      +446 -123  src/sys/dev/disk/aic7xxx/aic7xxx.c
  1.3       +28 -11    src/sys/dev/disk/aic7xxx/aic7xxx.h
  1.3       +4 -4      src/sys/dev/disk/aic7xxx/aic7xxx.reg
  1.3       +5 -4      src/sys/dev/disk/aic7xxx/aic7xxx.seq
  1.6       +28 -7     src/sys/dev/disk/aic7xxx/aic7xxx_93cx6.c
  1.3       +15 -15    src/sys/dev/disk/aic7xxx/aic7xxx_inline.h
  1.15      +47 -328   src/sys/dev/disk/aic7xxx/aic7xxx_osm.c
  1.10      +12 -296   src/sys/dev/disk/aic7xxx/aic7xxx_osm.h
  1.10      +92 -74    src/sys/dev/disk/aic7xxx/aic7xxx_pci.c

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