cvs commit: src/sys/i386/apic apic_abi.c apic_ipl.s apic_vector.s apicreg.h mpapic.c src/sys/i386/i386 db_interface.c exception.s mp_machdep.c mplock.s swtch.s src/sys/i386/icu icu_abi.c icu_ipl.s icu_vector.s src/sys/i386/include smp.h smptests.h ...

[Matthew Dillon]

dillon      2005/11/03 15:45:16 PST

DragonFly src repository

  Modified files:
    sys/i386/apic        apic_abi.c apic_ipl.s apic_vector.s 
                         apicreg.h mpapic.c 
    sys/i386/i386        db_interface.c exception.s mp_machdep.c 
                         mplock.s swtch.s 
    sys/i386/icu         icu_abi.c icu_ipl.s icu_vector.s 
    sys/i386/include     smp.h 
    sys/i386/isa         intr_machdep.c intr_machdep.h ipl.s 
    sys/sys              machintr.h 
  Removed files:
    sys/i386/include     smptests.h 
  Log:
  ICU/APIC cleanup part 9/many.
  
  Get rid of machine/smptests.h, remove or implement the related #defines.
  
  Distinguish between boot-time vector initialization and interrupt setup and
  teardown in MACHINTR ABI.
  
  Get rid of the ISR test for APIC-generated interrupts and all related
  support code.  Just generate the EOI and pray.
  
  Document more of the IO APIC redirection register(s).  Intel sure screwed up
  the LAPIC and IO APIC royally.  There is no simple way to poll the actual
  signal level on a pin, no simple way to manually EOI interrupts or EOI them
  in the order we desire, no simple way to poll the LAPIC for the vector that
  will be EOI'd when we send the EOI.  We can't mask the interrupt on the IO
  APIC without triggering stupid legacy code on some machines.  We can't even
  program the IO APIC linearly, it uses a stupid register/data sequence that
  makes it impossible for access on an SMP system without serialization.
  It's a goddamn mess, and it is all Intel's fault.
  
  Revision  Changes    Path
  1.7       +39 -14    src/sys/i386/apic/apic_abi.c
  1.15      +0 -1      src/sys/i386/apic/apic_ipl.s
  1.29      +2 -39     src/sys/i386/apic/apic_vector.s
  1.6       +108 -14   src/sys/i386/apic/apicreg.h
  1.12      +2 -9      src/sys/i386/apic/mpapic.c
  1.11      +0 -19     src/sys/i386/i386/db_interface.c
  1.26      +0 -1      src/sys/i386/i386/exception.s
  1.45      +4 -42     src/sys/i386/i386/mp_machdep.c
  1.18      +0 -1      src/sys/i386/i386/mplock.s
  1.40      +0 -1      src/sys/i386/i386/swtch.s
  1.6       +1 -0      src/sys/i386/icu/icu_abi.c
  1.14      +0 -1      src/sys/i386/icu/icu_ipl.s
  1.23      +0 -1      src/sys/i386/icu/icu_vector.s
  1.17      +0 -3      src/sys/i386/include/smp.h
  1.40      +1 -2      src/sys/i386/isa/intr_machdep.c
  1.22      +0 -10     src/sys/i386/isa/intr_machdep.h
  1.24      +0 -1      src/sys/i386/isa/ipl.s
  1.4       +3 -0      src/sys/sys/machintr.h


http://www.dragonflybsd.org/cvsweb/src/sys/i386/apic/apic_abi.c.diff?r1=1.6&r2=1.7&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/apic/apic_ipl.s.diff?r1=1.14&r2=1.15&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/apic/apic_vector.s.diff?r1=1.28&r2=1.29&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/apic/apicreg.h.diff?r1=1.5&r2=1.6&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/apic/mpapic.c.diff?r1=1.11&r2=1.12&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/i386/db_interface.c.diff?r1=1.10&r2=1.11&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/i386/exception.s.diff?r1=1.25&r2=1.26&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/i386/mp_machdep.c.diff?r1=1.44&r2=1.45&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/i386/mplock.s.diff?r1=1.17&r2=1.18&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/i386/swtch.s.diff?r1=1.39&r2=1.40&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/icu/icu_abi.c.diff?r1=1.5&r2=1.6&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/icu/icu_ipl.s.diff?r1=1.13&r2=1.14&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/icu/icu_vector.s.diff?r1=1.22&r2=1.23&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/include/smp.h.diff?r1=1.16&r2=1.17&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/isa/intr_machdep.c.diff?r1=1.39&r2=1.40&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/isa/intr_machdep.h.diff?r1=1.21&r2=1.22&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/isa/ipl.s.diff?r1=1.23&r2=1.24&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/sys/machintr.h.diff?r1=1.3&r2=1.4&f=u