Remove need for CPU_ENABLE_SSE option

Craig Dooley cd5697 at albany.edu
Mon Jul 28 06:35:08 PDT 2003


This patch removes the need for the CPU_ENABLE_SSE option in kernel configs.  
-- 
Craig Dooley						 cd5697 at xxxxxxxxxx
Index: conf/options.i386
===================================================================
RCS file: /home/dcvs/src/sys/conf/options.i386,v
retrieving revision 1.2
diff -u -r1.2 options.i386
--- conf/options.i386	17 Jun 2003 04:28:20 -0000	1.2
+++ conf/options.i386	28 Jul 2003 13:31:45 -0000
@@ -65,8 +65,6 @@
 CYRIX_CACHE_WORKS		opt_cpu.h
 CYRIX_CACHE_REALLY_WORKS	opt_cpu.h
 NO_MEMORY_HOLE			opt_cpu.h
-CPU_ENABLE_SSE			opt_cpu.h
-CPU_ATHLON_SSE_HACK		opt_cpu.h
 
 # The CPU type affects the endian conversion functions all over the kernel.
 I386_CPU		opt_global.h
Index: conf/options.pc98
===================================================================
RCS file: /home/dcvs/src/sys/conf/options.pc98,v
retrieving revision 1.2
diff -u -r1.2 options.pc98
--- conf/options.pc98	17 Jun 2003 04:28:20 -0000	1.2
+++ conf/options.pc98	28 Jul 2003 13:31:57 -0000
@@ -64,8 +64,6 @@
 CYRIX_CACHE_WORKS		opt_cpu.h
 CYRIX_CACHE_REALLY_WORKS	opt_cpu.h
 NO_MEMORY_HOLE			opt_cpu.h
-CPU_ENABLE_SSE			opt_cpu.h
-CPU_ATHLON_SSE_HACK		opt_cpu.h
 
 # The CPU type affects the endian conversion functions all over the kernel.
 I386_CPU		opt_global.h
Index: i386/conf/LINT
===================================================================
RCS file: /home/dcvs/src/sys/i386/conf/LINT,v
retrieving revision 1.2
diff -u -r1.2 LINT
--- i386/conf/LINT	17 Jun 2003 04:28:35 -0000	1.2
+++ i386/conf/LINT	28 Jul 2003 01:30:25 -0000
@@ -153,9 +153,6 @@
 #
 # Options for CPU features.
 #
-# CPU_ATHLON_SSE_HACK tries to enable SSE instructions when the BIOS has
-# forgotten to enable them.
-#
 # CPU_BLUELIGHTNING_FPU_OP_CACHE enables FPU operand cache on IBM
 # BlueLightning CPU.  It works only with Cyrix FPU, and this option
 # should not be used with Intel FPU.
@@ -177,8 +174,6 @@
 # reorder).  This option should not be used if you use memory mapped
 # I/O device(s).
 #
-# CPU_ENABLE_SSE enables SSE/MMX2 instructions support.
-#
 # CPU_FASTER_5X86_FPU enables faster FPU exception handler.
 #
 # CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
@@ -237,14 +232,12 @@
 # NOTE 3: This option may cause failures for software that requires
 # locked cycles in order to operate correctly.
 #
-options 	CPU_ATHLON_SSE_HACK
 options 	CPU_BLUELIGHTNING_FPU_OP_CACHE
 options 	CPU_BLUELIGHTNING_3X
 options 	CPU_BTB_EN
 options 	CPU_DIRECT_MAPPED_CACHE
 options 	CPU_DISABLE_5X86_LSSER
 options 	CPU_ELAN
-options 	CPU_ENABLE_SSE
 options 	CPU_FASTER_5X86_FPU
 options 	CPU_I486_ON_386
 options 	CPU_IORT
Index: i386/i386/initcpu.c
===================================================================
RCS file: /home/dcvs/src/sys/i386/i386/initcpu.c,v
retrieving revision 1.4
diff -u -r1.4 initcpu.c
--- i386/i386/initcpu.c	21 Jul 2003 07:57:43 -0000	1.4
+++ i386/i386/initcpu.c	28 Jul 2003 01:36:45 -0000
@@ -69,9 +69,7 @@
 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
 
-#ifdef CPU_ENABLE_SSE
 u_int	cpu_fxsr;		/* SSE enabled */
-#endif
 
 #ifdef I486_CPU
 /*
@@ -519,12 +517,10 @@
 void
 enable_sse(void)
 {
-#if defined(CPU_ENABLE_SSE)
-	if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
+	if ((cpu_feature & CPUID_SSE) && (cpu_feature & CPUID_FXSR)) {
 		load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
 		cpu_fxsr = hw_instruction_sse = 1;
 	}
-#endif
 }
 
 void
@@ -569,7 +565,6 @@
 				break;
 			}
 		} else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
-#if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK)
 			/*
 			 * Sometimes the BIOS doesn't enable SSE instructions.
 			 * According to AMD document 20734, the mobile
@@ -586,7 +581,6 @@
 				do_cpuid(1, regs);
 				cpu_feature = regs[3];
 			}
-#endif
 		}
 		break;
 #endif
Index: i386/i386/machdep.c
===================================================================
RCS file: /home/dcvs/src/sys/i386/i386/machdep.c,v
retrieving revision 1.30
diff -u -r1.30 machdep.c
--- i386/i386/machdep.c	26 Jul 2003 19:07:47 -0000	1.30
+++ i386/i386/machdep.c	28 Jul 2003 00:58:23 -0000
@@ -128,10 +128,8 @@
 extern void initializecpu(void);
 
 static void cpu_startup __P((void *));
-#ifdef CPU_ENABLE_SSE
 static void set_fpregs_xmm __P((struct save87 *, struct savexmm *));
 static void fill_fpregs_xmm __P((struct savexmm *, struct save87 *));
-#endif /* CPU_ENABLE_SSE */
 #ifdef DIRECTIO
 extern void ffs_rawread_setup(void);
 #endif /* DIRECTIO */
@@ -2263,7 +2261,6 @@
 	return (0);
 }
 
-#ifdef CPU_ENABLE_SSE
 static void
 fill_fpregs_xmm(sv_xmm, sv_87)
 	struct savexmm *sv_xmm;
@@ -2315,20 +2312,17 @@
 
 	sv_xmm->sv_ex_sw = sv_87->sv_ex_sw;
 }
-#endif /* CPU_ENABLE_SSE */
 
 int
 fill_fpregs(p, fpregs)
 	struct proc *p;
 	struct fpreg *fpregs;
 {
-#ifdef CPU_ENABLE_SSE
 	if (cpu_fxsr) {
 		fill_fpregs_xmm(&p->p_thread->td_pcb->pcb_save.sv_xmm,
 						(struct save87 *)fpregs);
 		return (0);
 	}
-#endif /* CPU_ENABLE_SSE */
 	bcopy(&p->p_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
 	return (0);
 }
@@ -2338,13 +2332,11 @@
 	struct proc *p;
 	struct fpreg *fpregs;
 {
-#ifdef CPU_ENABLE_SSE
 	if (cpu_fxsr) {
 		set_fpregs_xmm((struct save87 *)fpregs,
 				       &p->p_thread->td_pcb->pcb_save.sv_xmm);
 		return (0);
 	}
-#endif /* CPU_ENABLE_SSE */
 	bcopy(fpregs, &p->p_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
 	return (0);
 }
Index: i386/isa/npx.c
===================================================================
RCS file: /home/dcvs/src/sys/i386/isa/npx.c,v
retrieving revision 1.10
diff -u -r1.10 npx.c
--- i386/isa/npx.c	23 Jul 2003 02:30:19 -0000	1.10
+++ i386/isa/npx.c	28 Jul 2003 01:28:33 -0000
@@ -99,10 +99,8 @@
 #define	fnstsw(addr)		__asm __volatile("fnstsw %0" : "=m" (*(addr)))
 #define	fp_divide_by_0()	__asm("fldz; fld1; fdiv %st,%st(1); fnop")
 #define	frstor(addr)		__asm("frstor %0" : : "m" (*(addr)))
-#ifdef CPU_ENABLE_SSE
 #define	fxrstor(addr)		__asm("fxrstor %0" : : "m" (*(addr)))
 #define	fxsave(addr)		__asm __volatile("fxsave %0" : "=m" (*(addr)))
-#endif
 #define	start_emulating()	__asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
 				      : : "n" (CR0_TS) : "ax")
 #define	stop_emulating()	__asm("clts")
@@ -118,24 +116,17 @@
 void	fnstsw		__P((caddr_t addr));
 void	fp_divide_by_0	__P((void));
 void	frstor		__P((caddr_t addr));
-#ifdef CPU_ENABLE_SSE
 void	fxsave		__P((caddr_t addr));
 void	fxrstor		__P((caddr_t addr));
-#endif
 void	start_emulating	__P((void));
 void	stop_emulating	__P((void));
 
 #endif	/* __GNUC__ */
 
-#ifdef CPU_ENABLE_SSE
 #define GET_FPU_EXSW_PTR(pcb) \
 	(cpu_fxsr ? \
 		&(pcb)->pcb_save.sv_xmm.sv_ex_sw : \
 		&(pcb)->pcb_save.sv_87.sv_ex_sw)
-#else /* CPU_ENABLE_SSE */
-#define GET_FPU_EXSW_PTR(pcb) \
-	(&(pcb)->pcb_save.sv_87.sv_ex_sw)
-#endif /* CPU_ENABLE_SSE */
 
 typedef u_char bool_t;
 
@@ -508,11 +499,10 @@
 	 */
 	npxsave(&dummy);
 	stop_emulating();
-#ifdef CPU_ENABLE_SSE
 	/* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */
 	if (cpu_fxsr)
 		fninit();
-#endif
+	
 	fldcw(&control);
 	fpusave(&curthread->td_pcb->pcb_save);
 	start_emulating();
@@ -871,7 +861,7 @@
 npxsave(addr)
 	union savefpu *addr;
 {
-#if defined(SMP) || defined(CPU_ENABLE_SSE)
+#if defined(SMP)
 
 	stop_emulating();
 	fpusave(addr);
@@ -880,7 +870,7 @@
 	start_emulating();
 	mdcpu->gd_npxthread = NULL;
 
-#else /* SMP or CPU_ENABLE_SSE */
+#else /* SMP */
 
 	u_char	icu1_mask;
 	u_char	icu2_mask;
@@ -889,31 +879,39 @@
 	struct gate_descriptor	save_idt_npxintr;
 	u_long	save_eflags;
 
-	save_eflags = read_eflags();
-	cpu_disable_intr();
-	old_icu1_mask = inb(IO_ICU1 + 1);
-	old_icu2_mask = inb(IO_ICU2 + 1);
-	save_idt_npxintr = idt[npx_intrno];
-	outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
-	outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
-	idt[npx_intrno] = npx_idt_probeintr;
-	cpu_enable_intr();
-	stop_emulating();
-	fnsave(addr);
-	fnop();
-	start_emulating();
-	mdcpu->gd_npxthread = NULL;
-	cpu_disable_intr();
-	icu1_mask = inb(IO_ICU1 + 1);	/* masks may have changed */
-	icu2_mask = inb(IO_ICU2 + 1);
-	outb(IO_ICU1 + 1,
-	     (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
-	outb(IO_ICU2 + 1,
-	     (icu2_mask & ~(npx0_imask >> 8))
-	     | (old_icu2_mask & (npx0_imask >> 8)));
-	idt[npx_intrno] = save_idt_npxintr;
-	write_eflags(save_eflags); 	/* back to usual state */
+	/* Assume that if sse is enabled, then this bug is not present */
+	if(cpu_fxsr) {
+		stop_emulating();
+		fpusave(addr);
 
+		start_emulating();
+		mdcpu->gd_npxthread = NULL;
+	} else {
+		save_eflags = read_eflags();
+		cpu_disable_intr();
+		old_icu1_mask = inb(IO_ICU1 + 1);
+		old_icu2_mask = inb(IO_ICU2 + 1);
+		save_idt_npxintr = idt[npx_intrno];
+		outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
+		outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
+		idt[npx_intrno] = npx_idt_probeintr;
+		cpu_enable_intr();
+		stop_emulating();
+		fnsave(addr);
+		fnop();
+		start_emulating();
+		mdcpu->gd_npxthread = NULL;
+		cpu_disable_intr();
+		icu1_mask = inb(IO_ICU1 + 1);	/* masks may have changed */
+		icu2_mask = inb(IO_ICU2 + 1);
+		outb(IO_ICU1 + 1,
+		     (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
+		outb(IO_ICU2 + 1,
+		     (icu2_mask & ~(npx0_imask >> 8))
+		     | (old_icu2_mask & (npx0_imask >> 8)));
+		idt[npx_intrno] = save_idt_npxintr;
+		write_eflags(save_eflags); 	/* back to usual state */
+	}	
 #endif /* SMP */
 }
 
@@ -922,11 +920,9 @@
       union savefpu *addr;
 {
 
-#ifdef CPU_ENABLE_SSE
 	if (cpu_fxsr)
 		fxsave(addr);
 	else
-#endif
 		fnsave(addr);
 }
 
@@ -935,11 +931,9 @@
       union savefpu *addr;
 {
 
-#ifdef CPU_ENABLE_SSE
 	if (cpu_fxsr)
 		fxrstor(addr);
 	else
-#endif
 		frstor(addr);
 }
 
Index: i386/linux/linux_ptrace.c
===================================================================
RCS file: /home/dcvs/src/sys/i386/linux/linux_ptrace.c,v
retrieving revision 1.5
diff -u -r1.5 linux_ptrace.c
--- i386/linux/linux_ptrace.c	26 Jul 2003 18:12:43 -0000	1.5
+++ i386/linux/linux_ptrace.c	28 Jul 2003 01:32:28 -0000
@@ -215,7 +215,6 @@
 	l_long		padding[56];
 };
 
-#ifdef CPU_ENABLE_SSE
 static int
 linux_proc_read_fpxregs(struct proc *p, struct linux_pt_fpxreg *fpxregs)
 {
@@ -243,7 +242,6 @@
 		    sizeof(*fpxregs));
 	return (error);
 }
-#endif
 
 int
 linux_ptrace(struct linux_ptrace_args *uap)
@@ -339,15 +337,12 @@
 		}
 		break;
 	case PTRACE_SETFPXREGS:
-#ifdef CPU_ENABLE_SSE
 		error = copyin((caddr_t)uap->data, &r.fpxreg,
 		    sizeof(r.fpxreg));
 		if (error)
 			break;
-#endif
 		/* FALL THROUGH */
 	case PTRACE_GETFPXREGS: {
-#ifdef CPU_ENABLE_SSE
 		struct proc *p;
 
 		if (sizeof(struct linux_pt_fpxreg) != sizeof(struct savexmm)) {
@@ -411,9 +406,7 @@
 		break;
 
 	fail:
-#else
 		error = EIO;
-#endif
 		break;
 	}
 	case PTRACE_PEEKUSR:
Index: pc98/i386/machdep.c
===================================================================
RCS file: /home/dcvs/src/sys/pc98/i386/machdep.c,v
retrieving revision 1.6
diff -u -r1.6 machdep.c
--- pc98/i386/machdep.c	26 Jul 2003 21:35:27 -0000	1.6
+++ pc98/i386/machdep.c	28 Jul 2003 13:15:02 -0000
@@ -133,10 +133,8 @@
 extern void initializecpu(void);
 
 static void cpu_startup __P((void *));
-#ifdef CPU_ENABLE_SSE
 static void set_fpregs_xmm __P((struct save87 *, struct savexmm *));
 static void fill_fpregs_xmm __P((struct savexmm *, struct save87 *));
-#endif /* CPU_ENABLE_SSE */
 #ifdef DIRECTIO
 extern void ffs_rawread_setup(void);
 #endif /* DIRECTIO */
@@ -2293,7 +2291,6 @@
 	return (0);
 }
 
-#ifdef CPU_ENABLE_SSE
 static void
 fill_fpregs_xmm(sv_xmm, sv_87)
 	struct savexmm *sv_xmm;
@@ -2345,20 +2342,17 @@
 
 	sv_xmm->sv_ex_sw = sv_87->sv_ex_sw;
 }
-#endif /* CPU_ENABLE_SSE */
 
 int
 fill_fpregs(p, fpregs)
 	struct proc *p;
 	struct fpreg *fpregs;
 {
-#ifdef CPU_ENABLE_SSE
 	if (cpu_fxsr) {
 		fill_fpregs_xmm(&p->p_addr->u_pcb.pcb_save.sv_xmm,
 						(struct save87 *)fpregs);
 		return (0);
 	}
-#endif /* CPU_ENABLE_SSE */
 	bcopy(&p->p_addr->u_pcb.pcb_save.sv_87, fpregs, sizeof *fpregs);
 	return (0);
 }
@@ -2368,13 +2362,11 @@
 	struct proc *p;
 	struct fpreg *fpregs;
 {
-#ifdef CPU_ENABLE_SSE
 	if (cpu_fxsr) {
 		set_fpregs_xmm((struct save87 *)fpregs,
 					   &p->p_addr->u_pcb.pcb_save.sv_xmm);
 		return (0);
 	}
-#endif /* CPU_ENABLE_SSE */
 	bcopy(fpregs, &p->p_addr->u_pcb.pcb_save.sv_87, sizeof *fpregs);
 	return (0);
 }
Index: pc98/pc98/npx.c
===================================================================
RCS file: /home/dcvs/src/sys/pc98/pc98/npx.c,v
retrieving revision 1.4
diff -u -r1.4 npx.c
--- pc98/pc98/npx.c	10 Jul 2003 04:47:55 -0000	1.4
+++ pc98/pc98/npx.c	28 Jul 2003 13:30:59 -0000
@@ -103,10 +103,8 @@
 #define	fnstsw(addr)		__asm __volatile("fnstsw %0" : "=m" (*(addr)))
 #define	fp_divide_by_0()	__asm("fldz; fld1; fdiv %st,%st(1); fnop")
 #define	frstor(addr)		__asm("frstor %0" : : "m" (*(addr)))
-#ifdef CPU_ENABLE_SSE
 #define	fxrstor(addr)		__asm("fxrstor %0" : : "m" (*(addr)))
 #define	fxsave(addr)		__asm __volatile("fxsave %0" : "=m" (*(addr)))
-#endif
 #define	start_emulating()	__asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
 				      : : "n" (CR0_TS) : "ax")
 #define	stop_emulating()	__asm("clts")
@@ -122,24 +120,17 @@
 void	fnstsw		__P((caddr_t addr));
 void	fp_divide_by_0	__P((void));
 void	frstor		__P((caddr_t addr));
-#ifdef CPU_ENABLE_SSE
 void	fxsave		__P((caddr_t addr));
 void	fxrstor		__P((caddr_t addr));
-#endif
 void	start_emulating	__P((void));
 void	stop_emulating	__P((void));
 
 #endif	/* __GNUC__ */
 
-#ifdef CPU_ENABLE_SSE
 #define GET_FPU_EXSW_PTR(pcb) \
 	(cpu_fxsr ? \
 		&(pcb)->pcb_save.sv_xmm.sv_ex_sw : \
 		&(pcb)->pcb_save.sv_87.sv_ex_sw)
-#else /* CPU_ENABLE_SSE */
-#define GET_FPU_EXSW_PTR(pcb) \
-	(&(pcb)->pcb_save.sv_87.sv_ex_sw)
-#endif /* CPU_ENABLE_SSE */
 
 typedef u_char bool_t;
 
@@ -557,11 +548,9 @@
 	 */
 	npxsave(&dummy);
 	stop_emulating();
-#ifdef CPU_ENABLE_SSE
 	/* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */
 	if (cpu_fxsr)
 		fninit();
-#endif
 	fldcw(&control);
 	if (curpcb != NULL)
 		fpusave(&curpcb->pcb_save);
@@ -912,7 +901,7 @@
 npxsave(addr)
 	union savefpu *addr;
 {
-#if defined(SMP) || defined(CPU_ENABLE_SSE)
+#if defined(SMP)
 
 	stop_emulating();
 	fpusave(addr);
@@ -921,7 +910,7 @@
 	start_emulating();
 	mdcpu->gd_npxthread = NULL;
 
-#else /* SMP or CPU_ENABLE_SSE */
+#else /* SMP */
 
 	u_char	icu1_mask;
 	u_char	icu2_mask;
@@ -929,50 +918,58 @@
 	u_char	old_icu2_mask;
 	struct gate_descriptor	save_idt_npxintr;
 
-	disable_intr();
+	if(cpu_fxsr) {
+		stop_emulating();
+		fpusave(addr);
+
+		/* fnop(); */
+		start_emulating();
+		mdcpu->gd_npxthread = NULL;
+	} else {
+		disable_intr();
 #ifdef PC98
-	old_icu1_mask = inb(IO_ICU1 + 2);
-	old_icu2_mask = inb(IO_ICU2 + 2);
+		old_icu1_mask = inb(IO_ICU1 + 2);
+		old_icu2_mask = inb(IO_ICU2 + 2);
 #else
-	old_icu1_mask = inb(IO_ICU1 + 1);
-	old_icu2_mask = inb(IO_ICU2 + 1);
+		old_icu1_mask = inb(IO_ICU1 + 1);
+		old_icu2_mask = inb(IO_ICU2 + 1);
 #endif
-	save_idt_npxintr = idt[npx_intrno];
+		save_idt_npxintr = idt[npx_intrno];
 #ifdef PC98
-	outb(IO_ICU1 + 2, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
-	outb(IO_ICU2 + 2, old_icu2_mask & ~(npx0_imask >> 8));
+		outb(IO_ICU1 + 2, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
+		outb(IO_ICU2 + 2, old_icu2_mask & ~(npx0_imask >> 8));
 #else
-	outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
-	outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
+		outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
+		outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
 #endif
-	idt[npx_intrno] = npx_idt_probeintr;
-	enable_intr();
-	stop_emulating();
-	fnsave(addr);
-	fnop();
-	start_emulating();
-	mdcpu->gd_npxthread = NULL;
-	disable_intr();
-#ifdef PC98
-	icu1_mask = inb(IO_ICU1 + 2);	/* masks may have changed */
-	icu2_mask = inb(IO_ICU2 + 2);
-	outb(IO_ICU1 + 2,
-	     (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
-	outb(IO_ICU2 + 2,
-	     (icu2_mask & ~(npx0_imask >> 8))
-	     | (old_icu2_mask & (npx0_imask >> 8)));
-#else
-	icu1_mask = inb(IO_ICU1 + 1);	/* masks may have changed */
-	icu2_mask = inb(IO_ICU2 + 1);
-	outb(IO_ICU1 + 1,
-	     (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
-	outb(IO_ICU2 + 1,
-	     (icu2_mask & ~(npx0_imask >> 8))
-	     | (old_icu2_mask & (npx0_imask >> 8)));
+		idt[npx_intrno] = npx_idt_probeintr;
+		enable_intr();
+		stop_emulating();
+		fnsave(addr);
+		fnop();
+		start_emulating();
+		mdcpu->gd_npxthread = NULL;
+		disable_intr();
+#ifdef PC98
+		icu1_mask = inb(IO_ICU1 + 2);	/* masks may have changed */
+		icu2_mask = inb(IO_ICU2 + 2);
+		outb(IO_ICU1 + 2,
+	     	(icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
+		outb(IO_ICU2 + 2,
+	     	(icu2_mask & ~(npx0_imask >> 8))
+	     	| (old_icu2_mask & (npx0_imask >> 8)));
+#else
+		icu1_mask = inb(IO_ICU1 + 1);	/* masks may have changed */
+		icu2_mask = inb(IO_ICU2 + 1);
+		outb(IO_ICU1 + 1,
+	     	(icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
+		outb(IO_ICU2 + 1,
+	     	(icu2_mask & ~(npx0_imask >> 8))
+	     	| (old_icu2_mask & (npx0_imask >> 8)));
 #endif
-	idt[npx_intrno] = save_idt_npxintr;
-	enable_intr();		/* back to usual state */
-
+		idt[npx_intrno] = save_idt_npxintr;
+		enable_intr();		/* back to usual state */
+	}
 #endif /* SMP */
 }
 
@@ -981,11 +978,9 @@
       union savefpu *addr;
 {
 
-#ifdef CPU_ENABLE_SSE
 	if (cpu_fxsr)
 		fxsave(addr);
 	else
-#endif
 		fnsave(addr);
 }
 
@@ -994,11 +989,9 @@
       union savefpu *addr;
 {
 
-#ifdef CPU_ENABLE_SSE
 	if (cpu_fxsr)
 		fxrstor(addr);
 	else
-#endif
 		frstor(addr);
 }
 




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