[GSOC] Implement hardware nested page table support for vkernels
mihai.carabas at gmail.com
Mon Aug 5 11:34:47 PDT 2013
> At this point I have a single-core vkernel running in VMX non-root
> context, without sendmail. The sendmail is throwing an UD fault. I will
> investigate today and see what instruction is missing. Also I will
> implement the check for UD instruction (if it is "syscall" opcode or
> anything else). Another thing is modifying the vkernel a bit further in
> order to be able to run with multiple cores.
The sendmail problem was due to the fact that CR4_XSAVE wasn't enabled and
the instructions associated with it were thrown UD fault (e.g. "xgetbv") .
It was a little hard to find it because at first the db_disasm was letting
me know that the instruction was the "lgdt", but it was impossible (the
vkernel userspace doesn't execute this instruction). Than I manually
checked the byte code and saw in the Intel Reference Manual the
instruction. Also I've enriched the db_disasm code to recognize these new
group of instructions (the code is not so tightly coupled as the original
one -> should have a review before commiting to master).
Also I've implemented the support for multiple cores and is working ok in
some random situations. Due to race condition I think, the vkernel threads
enters in some infinit loops trying to solve some faults. I've spent the
last 3-4 days debugging this and with the help of Dillon and vsrinivas I
managed to advanced a little with the debugging, but the source of the bug
is unknown yet.
Also Dillon did a little refactoring to my code, modifying the way I cached
some attributes, in order to modify those attributes only and only when is
needed. I didn't integrate the code to my branch yet (I took only some
pieces of it). I will do this after I solve the bug.
After solving the bug, the next big steps are starting configuring EPT and
see what can I reuse from the "old" pmap code.
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