git: drm/i915: Disable caches for Global GTT.
ftigeot at crater.dragonflybsd.org
Sun Sep 13 04:08:32 PDT 2015
Author: FranÃ§ois Tigeot <ftigeot at wolfpond.org>
Date: Sun Sep 13 13:06:16 2015 +0200
drm/i915: Disable caches for Global GTT.
This is commit 76d0c9869b8cdbdb978caa4e13bc98840daafa2b from Linux 3.17.8
Original author: Rodrigo Vivi <rodrigo.vivi at intel.com>
Original commit message:
commit d6a8b72edc92471283925ceb4ba12799b67c3ff8 upstream.
Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000;
So the only way to avoid screen corruptions is setting PAT 0 to Uncached.
MOCS can still be used though. But if userspace is trusting PTE for
cache selection the safest thing to do is to let caches disabled.
BSpec: "For GGTT, there is NO pat_sel[2:0] from the entry,
so RTL will always use the value corresponding to pat_sel = 000"
- System agent ggtt writes (i.e. cpu gtt mmaps) already work before
this patch, i.e. the same uncached + snooping access like on gen6/7
seems to be in effect.
- So this just fixes blitter/render access. Again it looks like it's
not just uncached access, but uncached + snooping. So we can still
hold onto all our assumptions wrt cpu clflushing on LLC machines.
v2: Cleaner patch as suggested by Chris.
v3: Add Daniel's comment
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Cc: James Ausmus <james.ausmus at intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Jani Nikula <jani.nikula at intel.com>
Tested-by: James Ausmus <james.ausmus at intel.com>
Reviewed-by: James Ausmus <james.ausmus at intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
Signed-off-by: Jani Nikula <jani.nikula at intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Summary of changes:
sys/dev/drm/i915/i915_gem_gtt.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
DragonFly BSD source repository
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